x86_64: Optimize 128-bit TImode moves using SSE2
Improves 128-bit TImode moves between SSE and GPRs on x86_64 using SSE2, avoiding stack transfers.
This patch optimizes 128-bit TImode (128-bit integer) moves between SSE and general-purpose registers on x86_64 systems supporting SSE2. Previously, such moves often involved costly stack operations. The new implementation leverages SSE2’s shufpd instruction to perform these moves directly, reducing instruction count and improving performance. This is a partial fix for PR target/114544.
In Details
The x86_64 backend in GCC is updated to optimize *movti_internal for TImode on TARGET_SSE2 targets lacking TARGET_SSE4_1. The YD constraint in constraints.md is introduced to enable matching *movti_internal using SSE registers when SSE2 is available. This allows the split of TImode moves into movq (low half), shufpd (to position high half), and another movq (high half), bypassing stack memory transfers. The inline_secondary_memory_needed function in i386.cc is also updated.
- TImode
- GCC's internal representation mode for 128-bit integer types.
- SSE2
- Streaming SIMD Extensions 2, an instruction set extension for x86 architecture that adds support for 128-bit data manipulation.
- GPRs
- General-Purpose Registers, the primary registers used for arithmetic and data manipulation on a CPU.
- shufpd
- An SSE2 instruction that shuffles packed double-precision floating-point values, used here to manipulate 128-bit integer halves.
- Stack transfer
- Moving data between registers and the call stack, often used as a fallback when direct register-to-register operations are not efficient or available.