IRA: Treat hard register constraints like single register class constraints
Instruction Recognition and Allocation treats hard register constraints more consistently with register class constraints.
The Instruction Recognition and Allocation (IRA) pass now treats hard register constraints identically to constraints for single register classes. This change standardizes how operand constraints are processed, ensuring that register numbers are correctly computed for both types of constraints. The update simplifies logic within the process_single_reg_class_operands function and renames related helper functions for clarity. Some test cases were adjusted to account for potential changes in instruction selection and register allocation.
In Details
IRA's process_single_reg_class_operands now unifies handling for hard register constraints and single register class constraints by directly computing the register number. Previously, separate logic existed, potentially leading to inconsistencies. This simplifies the code and ensures that register allocation behaves predictably regardless of constraint type. The tests were updated because the cost model might now select different instruction alternatives due to more precise constraint handling.
- IRA
- Instruction Recognition and Allocation, a GCC optimization pass responsible for assigning hard registers to virtual registers.
- hard register constraint
- An assembler constraint that specifies a particular physical register that must be used for an operand.
- register class
- A set of registers that can be used interchangeably for a particular purpose or operand type.
- virtual register
- A temporary register used by the compiler during intermediate optimization passes, which is later mapped to a physical (hard) register.
- operand constraints
- Rules that specify the type and location of operands (inputs/outputs) for machine instructions, guiding the register allocator and instruction selector.