RISC-V: Allow RVV register overlap for vwmulsu.vv
RISC-V vwmulsu.vv instruction now supports register overlap, similar to other widen VV instructions.
This commit enables register overlap for the RISC-V Vector (RVV) vwmulsu.vv instruction. By leveraging the Wvr constraint in the machine description, this change allows vwmulsu.vv to reuse registers in a manner consistent with other widening vector instructions like vwadd.vv and vwsub.vv. This enhancement is expected to improve code density and potentially performance by enabling more efficient register utilization.
In Details
The machine description for RISC-V vector instructions has been updated to allow register group overlap for the vwmulsu.vv instruction. This is achieved by utilizing the Wvr constraint in vector.md. This change harmonizes the register usage semantics of vwmulsu.vv with other widening VV instructions, enabling the compiler to perform more aggressive register allocation and potentially reduce register spilling.
- RVV
- RISC-V Vector extension, a set of instructions designed to perform SIMD (Single Instruction, Multiple Data) operations on vectors of data.
- vwmulsu.vv
- A RISC-V Vector extension instruction for performing a widening multiply-accumulate operation on unsigned integers, with both source operands and the destination in vector registers.
- Wvr constraint
- A constraint used in GCC's machine description files that specifies register constraints related to widening vector operations, enabling more flexible register usage.