i386: Use insertps for SSE vector permutations
Improves SSE vector permutation performance on x86 by using the insertps instruction.
This patch enhances the i386 backend’s ability to implement vector permutations for V4SI and V4SF types by leveraging the SSE 4.1 insertps instruction. Previously, such operations resulted in multiple instructions; now, they can be consolidated into a single insertps instruction, significantly reducing code size and improving performance. This also aids in optimizing zero-extension operations for SSE registers.
In Details
The i386 backend's VEC_PERM_EXPR expansion for V4SI and V4SF vectors previously failed to recognize RTL patterns that could be efficiently implemented using SSE 4.1's insertps instruction. This patch adds four new define_insns to sse.md to cover all 16 permutation cases. The optimization simplifies expressions that extract an element from one vector and insert it into a vector of zeros. For example, a permutation like {x[0], 0, 0, 0} can now be generated using a single insertps instruction instead of several, improving performance and code density. This also provides a more efficien…
- VEC_PERM_EXPR
- An intermediate representation construct in GCC that represents a vector permutation operation, where elements of a vector are rearranged.
- V4SI
- A vector data type consisting of four 32-bit signed integers.
- V4SF
- A vector data type consisting of four 32-bit single-precision floating-point numbers.
- SSE
- Streaming SIMD Extensions, a set of instruction set extensions for x86 processors that enable parallel processing of data using SIMD instructions. SSE4.1 is a later revision that introduced new instructions like insertps.
- insertps
- An SSE 4.1 instruction that inserts a 32-bit value from a specified element of another XMM register into a specified element of the destination XMM register, potentially zeroing other elements.
- RTL
- Register Transfer Language, GCC's primary intermediate representation. It's a low-level, three-address code-like language used for optimizations and instruction selection.
- STV2 pass
- A compiler optimization pass, likely related to scalar-to-vector transformations or vector element extraction/insertion, that was not fully considering certain zero-extension patterns.