GCC Newspaper
OCTOBER 6, 2026
Date
/
Architectures
Components
Topics
News & Policy
Other
aarch64 Performance Win

aarch64: Use widening add instructions for sum reductions

Optimizes widening sum reductions on aarch64 by using [SU]ADDLP and [SU]ADALP, covering all SIMD shapes and improving performance.

This commit enhances the optimization of widening sum reductions on aarch64 by fully utilizing the [SU]ADDLP and [SU]ADALP instructions. It adds support for previously uncovered SIMD shapes and ensures that all power-of-two widening sum reductions are expressed efficiently. This change improves performance by reducing the number of operations required for these reductions, particularly for summing bytes into 64-bit accumulators.

In Details

The AArch64 SIMD reduction optabs for widening sums have been extended to cover all shapes using [SU]ADDLP and [SU]ADALP. The aarch64_expand_reduc_widen_sum now constructs chains using [SU]ADDLP for pairwise reduction and [SU]ADALP for accumulation. This addresses gaps in coverage, including V4SI <- V16QI and V2SI <- V8QI forms without dot product, and V2DI <- V8HI and V2DI <- V16QI forms, ensuring optimal instruction sequences for all relevant SIMD data types.

For Context
[SU]ADDLP
An AArch64 SIMD instruction that adds adjacent pairs of elements in a source vector and places the results in the next wider element size in the destination vector. It's used for widening sum operations.
[SU]ADALP
An AArch64 SIMD instruction similar to [SU]ADDLP, but it adds adjacent pairs of elements from two source vectors into the next wider element size in the destination vector. It's also used for widening sum operations.
Optabs
Optimization tables within GCC that map abstract operations to specific machine instructions or sequences of instructions.
SIMD
Single Instruction, Multiple Data. A class of parallel computers in Flynn's taxonomy. SIMD machines exploit data-level parallelism by performing the same operation on multiple data points simultaneously using specialized instructions.
V4SI <- V16QI
Represents a SIMD operation where 16 bytes (V16QI) are reduced to four 32-bit elements (V4SI) through a widening sum.
Filed Under: aarch64optimizationSIMD