RISC-V bit manipulation: Use BEXT for masked bit-test branches.
RISC-V bit manipulation: Replaces instruction sequence for masked bit-test branches with BEXT, reducing instruction count.
This commit optimizes RISC-V bit-test branches by utilizing the BEXT (Bit Extraction) instruction. Previously, masked bit tests with XLEN-wide indices involved a BSET and AND instruction pair before the branch. By matching the masked form of BEXT when the mask is XLEN-1, the compiler can now emit a single BEXT instruction followed by the branch, reducing the dynamic instruction count by approximately 0.5% on SPEC CPU 2017 Integer benchmark 541.leela_r.
In Details
The RISC-V Zbs extension's BSET/BCLR/BEXT instructions, when used for masked bit-test branches, have specific behaviors regarding the index mask. This commit refines the config/riscv/bitmanip.md pattern matching to correctly split masked bit-test branches into a single BEXT instruction when the input mask is XLEN - 1. This avoids an unnecessary BSET/AND sequence and simplifies instruction generation for these branches.
- RISC-V
- An open-standard instruction set architecture (ISA) based on reduced instruction set computing principles.
- Zbs extension
- A RISC-V bit manipulation extension that adds instructions for bit set, bit clear, and bit test operations.
- XLEN
- The native word size of the RISC-V architecture (e.g., 32 or 64 bits).
- BEXT
- RISC-V instruction for bit extraction. It extracts a contiguous sequence of bits from a source register.
- masked bit-test branches
- Conditional branches in RISC-V that test the state of a specific bit within a register, where the bit index might be masked.