i386: Disallow APX EGPR in FMA4/XOP instructions
Disallows use of extended general-purpose registers (EGPRs) in FMA4/XOP instructions on i386 to prevent unencodable instructions.
This commit prevents the use of APX EGPRs with FMA4 and XOP instructions on i386. These instructions are VEX-only and cannot be promoted to EVEX form. The change modifies instruction patterns to use a ‘jm’ constraint instead of ‘m’ and adds the ‘gpr16’ attribute to the address, thereby avoiding EGPR usage in specific scenarios and resolving an unencodable instruction issue.
In Details
This change addresses a specific instruction encoding limitation for VEX-encoded FMA4/XOP instructions on i386. The vex only alternatives in sse.md were being incorrectly generated with egpr in memory operands when -mapxf was enabled, leading to unencodable instructions. The fix replaces the memory constraint m with jm and specifies gpr16 for the address, ensuring that only standard registers are used for memory operands in these VEX-only instructions.
- APX
- Advanced Performance Extensions, a set of instructions for Intel processors.
- EGPR
- Extended General-Purpose Register, a newer set of wider registers available on some architectures.
- FMA4
- Fused Multiply-Add 4, an instruction set extension that performs fused multiply-add operations.
- XOP
- eXtended Operations, an instruction set extension that provides advanced vector operations.
- VEX
- Vector Extension, a prefix used to encode SIMD instructions with more than 2 operands.
- EVEX
- Enhanced Vector Extension, a more advanced prefix for encoding SIMD instructions, supporting more features than VEX.
- i386
- The 32-bit architecture of the Intel 80386 processor, forming the basis for x86.