xtensa: Discourage hardware FP registers for SFmode load/store
Xtensa backend prefers general-purpose registers over hardware FP registers for single-precision float loads/stores to reduce code size.
This commit modifies the Xtensa backend to prefer general-purpose registers (GPRs) over hardware floating-point registers (FPRs) for single-precision floating-point (SFmode) load and store operations. While functionally equivalent, using GPRs results in smaller code size when the Code Density Option is enabled. This is achieved by prefixing the hardware FP register constraints in the MD insn definition with an asterisk (’*’), signaling a lower priority. The change is demonstrated with an example showing reduced instruction encoding length for loads, stores, and immediate assignments.
In Details
Discourages use of hardware FP registers for SFmode load/store on Xtensa by prefixing register constraints with '*' in MD definitions. This prioritizes GPRs, which are more compact with the Code Density Option enabled, leading to smaller code size. Demonstrates reduction in instruction bytes for loads (l32i.n vs lsi) and assignments (movi.n vs const.s).
- xtensa
- A configurable processor architecture, often used in embedded systems. GCC includes a backend to generate code for various Xtensa configurations.
- SFmode
- GCC's internal representation for single-precision floating-point numbers (32-bit).
- MD insn definition
- An instruction definition within a GCC machine description (.md) file. These files specify the syntax, operands, and behavior of machine instructions for a target architecture.
- register constraints
- In GCC's MD files, these specify which types of registers can be used for a particular instruction operand. A '*' prefix indicates a lower priority or discouragement for using that register class.
- Code Density Option
- A configuration option for the Xtensa architecture that enables a more compact instruction encoding, reducing program size.