Removes RV64 optimization for bit clearing, simplifying code.
Removes a complex optimization for variable bit clearing on RISC-V RV64 due to correctness issues, simplifying the compiler's output.
This commit removes an optimization pass on RISC-V RV64 that aimed to replace sequences like addi+and with ctz+bclr for bit clearing operations. The optimization, intended to reduce instruction count, incorrectly handled 32-bit operations on 64-bit registers and produced incorrect sign extensions in some cases. By removing the problematic part of the pass, the compiler now correctly rejects this optimization when it cannot be safely applied, improving correctness for 32-bit operations on RV64.
In Details
The RISC-V bclr optimization pass, which targeted sequences like x & (x-1) with a nearby ctz to transform them into ctz + bclr, was found to be incorrect on RV64. Specifically, the x-1 step used 32-bit arithmetic while the subsequent logical and operated on the full 64-bit register, leading to incorrect sign extensions. This commit removes the problematic transformation by stripping out the SIGN_EXTEND elimination, allowing the combine pass to correctly reject the optimization. Support for 32-bit objects on rv64 is thus removed.
- bclr
- A RISC-V instruction that clears (sets to zero) a specified number of bits starting from a given position. It's often used in bit manipulation.
- ctz
- Count Trailing Zeros. An instruction or operation that counts the number of zero bits from the least significant bit up to the first set bit.
- RV64
- The 64-bit variant of the RISC-V instruction set architecture.
- sign extend
- An operation that extends a signed integer value to a larger data type by replicating the most significant bit (the sign bit). This preserves the number's sign.