arm: Ensure acquire barrier for RELEASE/ACQUIRE CAS.
ARM atomic compare-and-swap now correctly includes an acquire barrier for RELEASE/ACQUIRE memory orders.
This commit fixes a memory ordering issue on ARM for atomic compare-and-swap operations. When a success memory order of RELEASE and a failure memory order of ACQUIRE are used, the compiler previously failed to emit the necessary acquire barrier on the failure path for older ARM architectures (like ARMv6/v7) lacking specific load-acquire instructions. By removing a gate on TARGET_HAVE_LDACQ, the code now correctly promotes the memory model to ACQ_REL, ensuring both release and acquire semantics are preserved, thus resolving PR target/96056.
In Details
The arm_expand_compare_and_swap function in GCC's ARM backend incorrectly gated the promotion of the success memory model to ACQ_REL for the RELEASE/ACQUIRE combination on TARGET_HAVE_LDACQ. On targets without hardware load-acquire support (e.g., ARMv7), arm_split_compare_and_swap relied on DMB barriers. However, without the ACQ_REL promotion, the success model remained RELEASE, causing need_atomic_barrier_p to emit only the pre-barrier and omit the post-acquire barrier. This commit removes the TARGET_HAVE_LDACQ guard, ensuring the ACQ_REL promotion and the necessary acquire barri…
- atomic compare-and-swap (CAS)
- An atomic operation that reads a memory location, compares its value to an expected value, and if they match, writes a new value to that memory location. All in a single, indivisible step.
- memory order (RELEASE/ACQUIRE)
- Specifiers for atomic operations that define the visibility and ordering constraints of memory accesses relative to other threads. RELEASE ensures prior writes are visible to other threads performing an ACQUIRE operation.
- barrier (DMB)
- Data Memory Barrier. An instruction used on ARM processors to enforce ordering of memory operations between different observation points, ensuring that memory accesses become visible in a specific order.
- ARMv6/ARMv7
- Versions of the ARM architecture. ARMv7-A introduced features like load-acquire instructions, while earlier versions like ARMv7-A and ARMv6 may require explicit barriers for such ordering.