RISC-V: Add test cases for vwmacc.vv register overlap.
Adds extensive test cases for the RISC-V vwmacc.vv vector instruction, focusing on register group overlap.
This commit adds a comprehensive set of test cases for the RISC-V vwmacc.vv vector instruction, with a particular focus on register group overlap scenarios. Tests are generated for various data types (i8, i16, i32) and configurations (m1, m2, m4, mf2, mf4, mf8) to ensure correct functionality when source and destination registers overlap.
In Details
Expands RISC-V vector test coverage for vwmacc.vv, mirroring the efforts for vwmaccu.vv. This commit (along with 4f75092d25c099363892d03cb50b1142fb20bdcc) focuses on validating register group overlap for the vv-type multiply-accumulate instructions. The new tests in gcc/testsuite/ cover a wide range of data widths and vector element counts, ensuring the compiler correctly handles potential register conflicts and optimizations related to vwmacc.vv.
- vwmacc.vv
- A RISC-V vector instruction for a 2x16-bit to 32-bit multiply-accumulate operation, operating on vector registers.
- register group overlap
- A condition in RISC-V vector operations where the destination register group for an instruction might overlap with the source register group, requiring careful handling by the compiler and hardware.
- RISC-V Vector Extension (RVV)
- A set of instructions for the RISC-V architecture that enable efficient processing of vector and matrix data, crucial for high-performance computing and scientific applications.