RISC-V: Enable RVV register overlap for vw{add,sub,mul}[u].vv instructions
RISC-V Vector extension now supports register overlap for widened vector add, subtract, and multiply operations.
This commit enables register group overlap for several RISC-V Vector extension instructions: vwadd.vv, vwsub.vv, vwmul.vv, and their unsigned variants. This change allows these dual-widen vector instructions to leverage register overlap, similar to how vwadd[u].wv already does, potentially improving code density and performance.
In Details
This commit enables the Wvr constraint in the vector.md file for RISC-V, allowing register group overlap for the dual widen vector instructions vwadd[u].vv, vwsub[u].vv, and vwmul[u].vv. This extends the support for register overlap, previously available for vwadd[u].wv, to these vv variants, improving instruction scheduling flexibility.
- RISC-V Vector extension
- An extension to the RISC-V instruction set architecture that provides single instruction, multiple data (SIMD) capabilities for efficient vector processing.
- register overlap
- A condition in vector processing where the destination registers for an instruction's results may overlap with the source registers being read in the same instruction. This requires careful handling to avoid data corruption.
- Wvr constraint
- A constraint in GCC's machine description files (like vector.md) that specifies requirements for vector registers, in this case, enabling them to participate in register overlap operations.