x86: Remove SSE instructions that do not zero-extend
Removes SSE instructions from x86 target that incorrectly handled zero-extension.
This commit removes SSE instructions from the x86 target that were incorrectly implemented. Specifically, *fix_trunc<mode>si_sse_zext and *fix_trunc<mode>si_sse_2_zext did not perform the expected zero-extension of SImode to DImode. The changes also include a new test case to verify the fix.
In Details
Removes the *fix_trunc<mode>si_sse_zext and *fix_trunc<mode>si_sse_2_zext machine modes in i386.md. These modes were incorrectly implemented as they did not perform SImode to DImode zero-extension, unlike the SSE instructions CVTTSD2SI and CVTTSS2SI which have defined behavior for zero-extension depending on operand size and 64-bit mode. The fix ensures correctness for floating-point to integer conversions on x86. The affected PR is target/127045.
- SImode
- GCC's internal representation for a single integer precision mode, typically 32 bits.
- DImode
- GCC's internal representation for a double integer precision mode, typically 64 bits.
- zero-extend
- To expand a smaller integer to a larger one by filling the most significant bits with zeros. This is in contrast to sign-extension, which fills with the sign bit.
- CVTTSD2SI
- An SSE instruction that converts a scalar double-precision floating-point value to a signed doubleword integer, truncating towards zero. The behavior in 64-bit mode depends on the operand size.
- CVTTSS2SI
- An SSE instruction that converts a scalar single-precision floating-point value to a signed doubleword integer, truncating towards zero. The behavior in 64-bit mode depends on the operand size.