riscv: Restore previous --param=riscv-autovec-mode behaviour
Reverts a change that incorrectly modified RISC-V autovectorization mode.
This commit restores the intended behavior of the --param=riscv-autovec-mode option for the RISC-V architecture. A recent change had regressions that incorrectly altered the autovectorization mode. The fix ensures that the autovect mode is only overridden if it matches one of the available modes, preventing unintended modifications and regressions in RISC-V code generation.
In Details
Commit r17-4413-g3b99fd4bdc7005 introduced regressions in the RISC-V target by improperly handling the --param=riscv-autovec-mode setting. This change in config/riscv/riscv-v.cc now restores the previous behavior: the autovectorization mode is only overridden if the provided mode is actually present in the list of supported autovectorization modes (autovectorize_vector_modes).
- riscv-autovec-mode
- A GCC parameter that controls the autovectorization mode for the RISC-V architecture, influencing how the compiler utilizes vector instructions.
- autovectorization
- A compiler optimization technique that automatically transforms scalar code into vector code to utilize SIMD (Single Instruction, Multiple Data) instructions for increased performance.
- RISC-V
- An open-standard instruction set architecture (ISA) based on reduced instruction set computer principles.