FRIDAY, AUGUST 14, 2026
risc-v Performance Win
Allow RVV register overlap for vwmaccsu.vv.
RISC-V Vector extension now allows register overlap for the vwmaccsu.vv instruction.
Support for register overlap has been extended to the vwmaccsu.vv instruction in the RISC-V Vector extension. Similar to other widen ternary instructions, this commit enables the reuse of vector registers for vwmaccsu.vv, which handles mixed signed and unsigned narrowed sources, improving instruction scheduling flexibility.
In Details
The config/riscv/vector.md file has been updated to leverage the Wvr constraint, allowing register overlap for the vwmaccsu.vv instruction. This aligns its register usage semantics with other dual-widen ternary vector instructions like vwmacc[u].vv, providing more flexibility in instruction scheduling for vector code generation.
For Context
- RISC-V
- An open-standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles.
- RVV
- RISC-V Vector extension. An extension to the RISC-V ISA that provides support for single instruction, multiple data (SIMD) vector processing.
- vwmaccsu.vv
- A RISC-V Vector instruction for Multiply-Accumulate Signed-Unsigned, Vector-Vector. It performs a signed multiply on two source vectors, adds the result to a third vector, and stores it in a destination vector. The 'su' indicates signed source 1 and unsigned source 2.
- register overlap
- A situation in vector processing where different operations might use the same physical registers, potentially leading to data dependencies or requiring careful management of register lifetimes.
- Wvr constraint
- A constraint in GCC's machine description (MD) files used for RISC-V vector operations, indicating that a register can be used for both read and write operations, allowing for register overlap.