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OCTOBER 6, 2026
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gcc/x86 Performance Win

x86 SSE vector initialization improved for V4SF type.

Optimized x86 SSE code generation for V4SF vector initialization, fixing a performance regression.

This commit addresses a performance regression in x86 SSE vector initialization for the V4SF type. The previous update inadvertently caused issues with implicit zero extension when a value was already in a register. The fix introduces improved register preferencing and utilizes idioms like pslldq/psrldq for more efficient initialization, reducing inter-unit moves and matching LLVM’s approach.

In Details

This patch revises vec_set<mode>_0's define_insn on x86 to avoid expensive inter-unit moves for V4SF initialization. When V4SF{x, 0, 0, 0} is required, it now prefers using SSE instructions like pxor and movss to achieve zero-extension, rather than costly transfers to GPRs. For cases without zero-extension, it retains the vec_concat idiom. It also optimizes memory loads with onevar_perm and shufps.

For Context
SSE
Streaming SIMD Extensions, a set of CPU instructions designed to perform single-instruction, multiple-data (SIMD) operations on data in parallel. Used here for vector processing.
V4SF
A vector data type consisting of four single-precision floating-point numbers.
zero extension
A process where a smaller value is widened to a larger data type, with the new bits filled with zeros. This is crucial for correctly initializing vector elements.
inter-unit move
A data transfer between different types of CPU registers, such as between a general-purpose register (GPR) and an SSE/AVX vector register. These moves can be slower than moves within the same register class.
GPR
General-Purpose Register. A register in the CPU that can be used for various purposes, such as holding data or addresses.
movss
SSE instruction to move a single-precision scalar floating-point value.
pslldq
SSE instruction to perform a left logical shift of packed data by a quadword (16 bytes).
psrldq
SSE instruction to perform a right logical shift of packed data by a quadword (16 bytes).
Filed Under: x86sseoptimizationcompiler