RISC-V: Add test cases for vwmaccu.vv register overlap.
Adds numerous test cases for the RISC-V vwmaccu.vv vector instruction, focusing on register group overlap scenarios.
This commit introduces a comprehensive suite of test cases for the RISC-V vwmaccu.vv vector instruction, specifically targeting register group overlap. A variety of data types (u8, u16, u32) and different mask/element counts (m1, m2, m4, mf2, mf4, mf8) are covered to ensure the instruction behaves correctly when destination and source registers overlap.
In Details
Expands RISC-V vector test coverage for vwmaccu.vv. This commit (along with 55afdf36b7a2acd881c93485ce2af6d1cf006e18) specifically targets register group overlap for the vv-type multiply-accumulate instructions. The tests in gcc/testsuite/verify the correct implementation of vwmaccu.vv across various vector length configurations and data widths, ensuring that the compiler can effectively utilize overlapping registers for performance when permitted by the architecture.
- vwmaccu.vv
- A RISC-V vector instruction for a 2x16-bit to 32-bit unsigned multiply-accumulate operation, operating on vector registers.
- register group overlap
- A condition in RISC-V vector operations where the destination register group for an instruction might overlap with the source register group, requiring careful handling by the compiler and hardware.
- RISC-V Vector Extension (RVV)
- A set of instructions for the RISC-V architecture that enable efficient processing of vector and matrix data, crucial for high-performance computing and scientific applications.