RISC-V: Allow RVV register overlap for vwmaccus.vx
Enables register overlap for RISC-V vector multiply-accumulate instruction, removing test case xfails.
This change enables register overlap for the RISC-V vector instruction vwmaccus.vx, similar to other widen ternary vx instructions. By leveraging the Wvr constraint in the machine description, the compiler can now allow these registers to overlap, which previously caused related test cases to fail. This allows for more flexible register allocation and simplifies testing.
In Details
This commit modifies the RISC-V vector instruction definitions (vector.md) to allow register overlap for the vwmaccus.vx instruction, specifically by using the Wvr constraint. This aligns vwmaccus.vx with other widen ternary vx instructions like vwmacc[u].vx and vwmaccsu.vx in terms of register allocation flexibility. Consequently, previously xfailed test cases related to this instruction are now expected to pass.
- vwmaccus.vx
- A RISC-V vector instruction for performing a fused multiply-accumulate operation with a vector source and a scalar destination, potentially with wider intermediate results.
- RVV
- RISC-V Vector extension, a set of instructions designed for high-performance data-parallel processing.
- register overlap
- A situation where different instructions or operations can safely use the same physical registers without causing data conflicts, allowing for more efficient register allocation.
- Wvr constraint
- A specific constraint used in GCC's machine description files (like vector.md) to indicate that a register can be used for widen vector operations, potentially allowing for overlap with other similar operations.