THURSDAY, AUGUST 20, 2026
risc-v Performance Win
RISC-V: Allow RVV register overlap for vw{add,sub,mul}[u].vx
Enables RISC-V vector extension register overlap for dual-widen vx instructions like vwadd.vx.
The RISC-V vector extension now allows register overlap for dual-widen vx instructions, including vwadd[u].vx, vwsub[u].vx, and vwmul[u].vx. This change leverages the ‘Wvr’ constraint in the vector configuration, potentially improving instruction scheduling and register utilization.
In Details
This commit modifies config/riscv/vector.md to allow register overlap for dual-widen vx instructions in the RISC-V Vector extension (RVV). It achieves this by leveraging the Wvr constraint, enabling more flexible instruction scheduling and register allocation for these operations.
For Context
- RVV
- The RISC-V Vector extension, an optional feature for the RISC-V instruction set architecture that provides wide vector registers and instructions for high-performance computing.
- vwadd.vx, vwsub.vx, vwmul.vx
- RISC-V Vector instructions that perform widened signed addition, subtraction, or multiplication with a scalar element, storing the result in a vector register. The '.vx' suffix indicates the second operand is a scalar.
- Register overlap
- A situation where instructions can reuse or share register resources without conflict, potentially improving code density and performance.
- Wvr constraint
- A constraint used in GCC's machine descriptions to specify requirements related to vector register usage, particularly for widened operations.