RISC-V: Allow RVV register overlap for vfwadd.wv
Compiler now permits specific register overlap scenarios for the RISC-V vector `vfwadd.wv` instruction.
This commit adjusts constraints for the RISC-V vector vfwadd.wv instruction to allow certain register overlaps. Previously, the instruction had strict constraints regarding operand register overlap. New constraints (Wn4 and Wvr) are introduced and applied to operands vs1 and vs2 respectively, enabling cases where the narrow operand vs1 might fall within the vs2 register group, provided it doesn’t overlap the entire vs2 group.
In Details
The vfwadd.wv instruction has specific register constraints that were previously too restrictive. This commit modifies config/riscv/constraints.md and config/riscv/vector.md to allow for register overlap scenarios. Specifically, a new constraint Wn4 is defined to permit operand 4 (implicitly vs1 in some forms) to overlap with the destination register vd, as long as it doesn't overlap with vs2. The vfwadd.wv instruction's operand 3 (likely vs2) is assigned the Wvr constraint, and operand 4 (likely vs1) is assigned the new Wn4 constraint. This resolves issues where the n…
- RISC-V vector extension (RVV)
- An extension to the RISC-V instruction set architecture that provides support for vector (SIMD) operations, enabling single instructions to operate on multiple data elements simultaneously for improved performance in data-parallel tasks.
- vfwadd.wv
- A RISC-V vector instruction for fused multiply-add operations, specifically a 'widening floating-point add' where the vector elements are widened before addition. The 'wv' suffix likely indicates specific operand constraints or behavior.
- register overlap
- A situation in instruction scheduling or code generation where two or more distinct register allocations occupy the same physical registers at different points in time, or where an instruction's operands refer to registers that partially or wholly overlap with each other or with destination registers.
- constraint
- In the context of compiler backends, a constraint specifies the valid types of operands (e.g., registers, memory locations, immediate values) that an instruction can accept. These are often defined in machine description files.