RISC-V: Prepare core table for identification registers
The RISC-V core table structure is updated to accommodate CPU identification registers.
The RISC-V core identification table structure has been modified to include space for MVENDORID, MARCHID, and MIMPID registers. Initially, these fields are set to UNKNOWN_ID for all cores, preparing the system for later population with specific CPU identification values, which is necessary for features like -mcpu=native.
In Details
This commit refactors the RISC-V core identification mechanism by updating riscv-cores.def and related files. It introduces riscv_core_id_t and modifies the RISCV_CORE macro to accept MVENDORID, MARCHID, and MIMPID. All existing cores are initially assigned UNKNOWN_ID for these fields, simplifying future additions of specific CPU identification data needed for CPU feature detection.