aarch64: Introduce and employ the extsize iterator for instruction suffixes
New 'extsize' iterator improves instruction pattern matching for aarch64 by distinguishing between extension and load/store suffixes.
The aarch64 backend has introduced a new extsize iterator to correctly represent instruction suffixes for 32-bit operations. Previously, the generic size iterator was used for both extension instructions (like uxtw) and load/store instructions, incorrectly expanding to ‘w’ for 32-bit modes in the latter case. The extsize iterator expands to ‘w’ for extensions but an empty string for loads/stores, resolving issues with instructions like ldrw or strw which do not exist. This change ensures accurate pattern matching for SIMD and general-purpose instructions that have distinct suffixes for extensions versus memory operations.
In Details
Introduces the extsize iterator for the aarch64 backend to distinguish instruction suffix behavior between sign/zero extensions and loads/stores. The size iterator incorrectly yielded 'w' for 32-bit ldr/str patterns, which are invalid mnemonics. extsize expands to '' for 32-bit loads/stores and 'w' for uxtw/sxtw, fixing pattern matching in aarch64.md and aarch64-simd.md.
- iterator
- In the context of GCC's machine description files (MD), an iterator is a placeholder that expands to different values based on the target mode or configuration. It's used to generate multiple instruction patterns concisely.
- aarch64
- The 64-bit ARM architecture, commonly used in mobile devices and increasingly in servers and desktops. GCC has a specific backend for generating code for this architecture.
- SFmode
- GCC's internal representation for single-precision floating-point numbers (32-bit).
- MD insn definition
- An instruction definition within a GCC machine description (.md) file. These files specify the syntax, operands, and behavior of machine instructions for a target architecture.
- register constraints
- In GCC's MD files, these specify which types of registers can be used for a particular instruction operand. A '*' prefix indicates a lower priority or discouragement for using that register class.