x86-64: Correct SSE feature check for pinsrq/pextrq
Fixes SSE feature check for `pinsrq`/`pextrq` instructions on x86-64.
This commit corrects a feature check for the SSE instructions pinsrq and pextrq on x86-64. Previously, the compiler incorrectly checked for the AVX feature instead of the SSE4.1 feature, which is when these instructions were introduced. This ensures that the compiler correctly identifies and utilizes these instructions.
In Details
Corrects the feature check in timode_scalar_chain::compute_convert_gain for pinsrq and pextrq. The commit was checking TARGET_AVX which is incorrect, as these instructions were introduced in SSE4.1. The check is now correctly set to TARGET_SSE4_1. This resolves PR target/127020 by ensuring correct codegen for TImode scalar value conversions using these instructions.
- pinsrq
- An SSE4.1 instruction that inserts a quadword register into a double quadword register at a specified offset.
- pextrq
- An SSE4.1 instruction that extracts a quadword from a double quadword register at a specified offset.
- TImode
- GCC's internal representation for a double integer precision mode, typically 64 bits.
- STV
- Scalar Target Value. Likely refers to scalar operations on vector or larger-than-register types.
- TARGET_AVX
- A GCC target feature flag indicating support for Advanced Vector Extensions (AVX) instructions.
- TARGET_SSE4_1
- A GCC target feature flag indicating support for SSE4.1 instructions.