RISC-V: Add tests for widening instruction ICE
Adds test cases to expose and verify fixes for compiler internal errors with RISC-V widening instructions.
This commit introduces a suite of test cases for the RISC-V Vector (RVV) extension, specifically targeting an internal compiler error (ICE) that occurred with widening instructions. The ICE was triggered when the destination and source registers of a widening instruction had the same number of registers, leading to incorrect assertion failures in the compiler’s reload pass. These new tests ensure that such scenarios are correctly handled and prevent regressions.
In Details
This commit adds test cases for an ICE in the RISC-V backend, related to widening vector instructions (e.g., vwmul.vv). The issue, tracked in PR target/127269, occurs when the destination and source operands of a widening instruction have the same number of registers, and the compiler's riscv_v_widen_constraint_ok function incorrectly asserts nregs == 1. The tests verify the fix where this condition is now handled by returning false instead of asserting when nregs > 1.
- RISC-V
- An open standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles.
- RVV
- The RISC-V Vector extension, which provides single instruction, multiple data (SIMD) capabilities for high-performance computing.
- widening instruction
- A vector instruction that operates on data elements of one size and produces results with larger data elements, effectively widening the data.
- ICE
- Internal Compiler Error, a condition where the compiler encounters an unexpected state and terminates instead of producing code.
- LMUL
- Lane multiplier in the RISC-V Vector extension, which determines the number of vector register elements that form a single vector register.
- nregs
- In the context of RISC-V vector instructions, this likely refers to the number of vector registers required to hold the entire vector operand.
- reload pass
- A compiler pass, typically in the backend, responsible for handling register allocation and instruction selection, often involving Spill/Fill operations.