THURSDAY, SEPTEMBER 3, 2026
amdgcn Performance Win
amdgcn: Improve DImode "not" instruction.
The AMDGCN backend now uses a more efficient instruction for DImode 'not' operations.
The AMDGCN backend’s handling of the bitwise NOT operation for DImode (64-bit integers) has been improved. Instead of requiring two instructions, it now uses the s_not_b64 instruction, making the operation more efficient.
In Details
This commit modifies the AMDGCN backend's instruction selection for DImode (64-bit integer) bitwise NOT operations. Previously, the one_cmpldi2 pattern in gcn.md might have expanded to multiple instructions. This change refactors it to directly use the s_not_b64 machine instruction, which performs a 64-bit bitwise NOT in a single cycle, improving instruction density and potentially performance.
For Context
- amdgcn
- A specific target architecture for AMD graphics cards, for which GCC can generate code. The code generation for this target resides in the
amdgcnbackend. - DImode
- In GCC's internal representation, this refers to a 64-bit integer type. 'DI' stands for 'double int'.
- bitwise NOT
- A logical operation that inverts each bit of its operand. If a bit is 0, it becomes 1; if it is 1, it becomes 0.
- s_not_b64
- A specific AMD GCN assembly instruction that performs a bitwise NOT operation on a 64-bit register.