RISC-V: Improve __builtin_bitreverse code generation with ZBKB extension.
RISC-V __builtin_bitreverse functions now use more efficient instructions when the ZBKB extension is enabled.
GCC improves code generation for __builtin_bitreverse{8,16,32,64} on RISC-V when the ZBKB extension is enabled. It now utilizes specific brev8 or rev8 instructions for better performance. The change also adjusts the condition for using the bswaphi2 instruction to include the ZBKB extension.
In Details
The RISC-V backend's bit manipulation support has been updated. The __builtin_bitreverse family of intrinsics now correctly maps to the brev8 or rev8 instructions when the Zbb or Zbs extensions (specifically zbkb as indicated by the patch) are available. The bswaphi2 expander's condition was broadened from TARGET_ZBB to TARGET_ZBB || TARGET_ZBKB for consistency.