Add AVX10/v2 intrinsics for sub-byte element extraction and symmetric-signed saturation narrowing.
New AVX10/v2 intrinsics enable efficient sub-byte data manipulation and saturation operations.
This commit introduces support for new AVX10/v2 instructions related to sub-byte element extraction and symmetric-signed saturation narrowing. It adds new intrinsic functions for various vector sizes (128, 256, and 512 bits) to handle these operations, along with necessary definitions in i386-builtin-types.def, i386-builtin.def, and i386-expand.cc. New patterns in sse.md facilitate the implementation of these instructions.
In Details
Introduces AVX10/v2 intrinsics (_mm_cvtss_epi32_epi8, _mm_unpack_epi8, etc.) into GCC's x86 backend. These intrinsics map to new AVX10/v2 instructions for sub-byte data processing and saturation. The changes span multiple files including header definitions, built-in descriptions, expansion routines, and machine description patterns, ensuring proper code generation for these advanced SIMD operations.
- AVX10/v2
- An extension to the AVX (Advanced Vector Extensions) instruction set architecture, providing new capabilities for high-performance computing, particularly in areas like sub-byte data manipulation and saturation arithmetic.
- Intrinsics
- Special functions that provide a C/C++ interface to low-level hardware instructions, allowing developers to leverage specific CPU capabilities directly from high-level code.
- Sub-byte element extraction
- Operations that extract smaller data units (less than a byte, e.g., nibbles or bits) from larger vector registers.
- Symmetric-signed saturation narrowing
- A type of arithmetic operation where results that exceed the representable range are clamped to the maximum or minimum representable value. 'Symmetric-signed' implies clamping for both positive and negative overflows.
- Vector registers
- Specialized CPU registers that can hold multiple data elements (e.g., integers, floating-point numbers) simultaneously, enabling Single Instruction, Multiple Data (SIMD) operations for parallel processing.