Fixes incorrect code generation for aarch64 max/min-of-add/sub.
Ensures correct condition code handling for aarch64 conditional selects.
A bug in aarch64 code generation for max/min-of-add/sub patterns caused incorrect results by not properly indicating that these instructions clobber condition codes. This led to the compiler removing necessary comparison instructions, resulting in a conditional select (csel) using stale flags. The fix adds a (clobber (reg:CC CC_REGNUM)) to the relevant instruction patterns, ensuring that condition codes are correctly marked as modified. This preserves the necessary comparison instructions and resolves the miscompilation.
In Details
AArch64's max/min-of-add/sub patterns, implemented using ADDS/SUBS followed by CSEL, were missing a (clobber (reg:CC CC_REGNUM)) in their MD definitions. This omission caused the scheduler and combiner to incorrectly assume that condition codes were preserved, leading to the removal of preceding compare instructions. Consequently, the CSEL would operate on stale flags, causing incorrect results. Adding the clobber dependency resolves this by correctly signaling that the condition codes are written by these instructions, ensuring preceding comparisons are retained.
- aarch64
- The 64-bit ARM architecture, a widely used instruction set architecture for mobile and server processors.
- condition codes
- Flags (like zero, carry, negative, overflow) set by arithmetic or comparison instructions, used by subsequent conditional branch or select instructions.
- CC_REGNUM
- The specific register number in the aarch64 architecture that holds the condition code flags.
- CSEL
- Conditional Select instruction on ARM architectures. It selects one of two source registers based on the condition codes and writes the result to a destination register.
- MD definition
- Machine Description file entries that define the behavior, operands, and constraints for specific processor instructions used by the compiler's backend.