x86-64: Enable 128-bit atomic operations by default
Adds -m128bit-atomic flag and enables it by default on compatible x86-64 CPUs to improve performance of 128-bit atomic loads/stores.
This commit introduces the -m128bit-atomic compiler option, allowing the generation of inline 128-bit atomic loads and stores. This avoids the overhead of calling into the libatomic library for platforms that support these operations. The option is now enabled by default in 64-bit mode for processors supporting x86-64-v3 or later, or AVX-capable processors from major vendors, simplifying the use of efficient atomic operations for developers targeting compatible hardware.
In Details
The -m128bit-atomic option has been introduced for x86-64 targets, enabling the use of 128-bit atomic loads and stores directly via instructions like movti. This option is enabled by default for 64-bit mode on processors meeting specific compatibility criteria (x86-64-v3, or AVX-capable Intel/AMD/Hygon/Zhaoxin CPUs), as detailed in the associated bug reports. The option also implicitly enables -mcx16 when used, and the TARGET_128BIT_ATOMIC_ENABLED macro controls its runtime availability.
- libatomic
- A library that provides atomic built-in functions for C, C++, and Fortran, allowing programmers to perform atomic operations on various data types. These operations are often implemented using specific hardware instructions when available, otherwise falling back to library routines.
- x86-64-v3
- A microarchitecture compatibility level for x86-64 processors. Level 3 implies support for a specific set of advanced instructions, including AVX, AVX2, FMA, and others, which are beneficial for performance-intensive tasks.
- AVX
- Advanced Vector Extensions. An extension to the x86 instruction set architecture for microprocessors, introduced by Intel. AVX instructions use a 256-bit YMM register and can perform vectorized operations on floating-point data.
- Atomic operations
- Operations that are guaranteed to execute indivisibly. In concurrent programming, atomic operations prevent race conditions by ensuring that a sequence of operations appears to occur instantaneously from the perspective of other threads or processes.