AArch64 supports rounding narrowing shifts at source width.
Enables AArch64 to match rounding narrowing shift instructions written at the source data width.
This change introduces new AArch64 instruction patterns to match rounding narrowing shifts (RSHRN) when the operation is expressed at the source data width, rather than requiring a wider intermediate representation. This improves code generation for common narrowing operations, reducing instruction counts in areas like video encoding and media processing.
In Details
This commit adds new RTL patterns for AArch64's RSHRN (rounding shift right and narrow) instruction, specifically for source-width operations. Previously, RSHRN was primarily matched through ACLE intrinsics that operated on widened operands. The new patterns allow combine to recognize (x + (1 << (n - 1))) >> n when narrowing, where x is at the source width. This enables optimization of code that performs rounding and narrowing in a single conceptual step, improving performance in media codecs and other SIMD-intensive applications. Saturating variants (SQRSHRN, UQRSHRN) remain un…
- RSHRN
- AArch64 SIMD instruction that performs a rounding shift right and narrows the result to half the element width.
- ACLE
- ARM C Language Extension, providing intrinsic functions for specific ARM architecture features.
- V2XWIDE
- Refers to a vector data type that is twice the width of the source elements, used for intermediate calculations in SIMD operations.
- combine
- An optimization pass in GCC that performs instruction combination and simplification on RTL.