ARM: Fix missed optimization for lsls instruction
Corrects a regression in GCC's ARM backend that prevented the use of the efficient 'lsls' instruction on Thumb.
A recent change intended to fix PR tree-optimization/123236 inadvertently caused a regression in GCC’s ARM backend, specifically affecting Thumb code. The compiler now fails to emit the shorter lsls instruction for a particular optimization pattern, leading to less efficient code. This commit disables the offending transformation in the combine pass, resolving the issue and allowing GCC to generate the expected, more optimal RTL that matches ARM’s Thumb instruction set.
In Details
A regression introduced by a prior change related to PR tree-optimization/123236 caused combine to generate suboptimal RTL for ARM Thumb targets. Specifically, the pattern involving (set (reg:SI ... ) (and:QI ...)) followed by a comparison was being translated in a way that prevented matching the efficient lsls instruction. This commit disables the problematic transformation in combine, restoring the ability to match the correct Thumb instruction by generating more suitable RTL, likely involving zero_extract.
- RTL (Register Transfer Language)
- GCC's intermediate representation used after GIMPLE. It describes operations in terms of registers and memory locations, closer to machine code but still abstract.
- lsls instruction
- A Thumb (ARM's 16-bit instruction set) instruction for logical shift left, often smaller and faster than its general-purpose equivalent.
- Combine pass
- A GCC optimization pass that attempts to merge or simplify sequences of RTL instructions into more efficient forms.
- WORD_REGISTER_OPERATIONS
- A target-specific option in GCC that indicates whether the architecture supports operations on operands wider than the native word size (e.g., 32-bit operations on a 16-bit machine).
- ARM
- A widely used family of Reduced Instruction Set Computer (RISC) architectures, common in mobile devices and embedded systems.
- Thumb
- A 16-bit instruction set architecture for ARM processors, designed for code density. It is a subset of the full ARM instruction set.