Initial support for ACEv1
Adds foundational support for the ACEv1 instruction set, enabling its recognition and basic option handling.
This commit lays the groundwork for ACEv1 support in GCC by introducing initial configurations and option handling. It adds ACEv1 to the CPU feature list, defines associated compiler options, and updates internal ISA definitions. Documentation for ACEv1 is also included in the GCC manuals. This sets the stage for subsequent commits that will add specific instruction support.
In Details
Establishes initial compiler support for the ACEv1 instruction set architecture. This involves registering FEATURE_ACEV1 in i386-cpuinfo.h, defining OPTION_MASK_ISA2_ACEV1_SET and _UNSET in i386-common.cc, and handling these options in ix86_handle_option. ACEv1 is added to i386-isa.def and macev1 option is introduced in i386.opt. CPUID bit bit_ACE is defined. This commit primarily focuses on CPU feature detection and command-line option processing, paving the way for instruction-level implementation.
- ACEv1
- AI Compute Extensions version 1, a new x86 instruction set architecture designed for AI and compute-intensive workloads.
- ISA
- Instruction Set Architecture, the set of commands a particular processor can understand and execute.
- CPUID
- An x86 instruction that provides information about the CPU's features and capabilities, used by software to detect supported instruction sets.