amdgcn: Add vector widening multiply instructions
New vector widening multiply instructions are added to the AMDGPU backend, matching existing scalar functionality.
This commit introduces new vector widening multiply instructions to the AMDGPU backend, mirroring the scalar widening multiply instructions already present. Additionally, a scalar multiply instruction has been renamed to adhere to standard naming conventions. These additions enhance the instruction set available for AMD GPU code generation.
In Details
The AMDGPU backend's instruction selection (gcn-valu.md and gcn.md) is enhanced with new machine definitions for vector widening multiply instructions (mul<mode><vnsi>3<exec>, mul<mode><vnhi>3<exec>). This follows the addition of scalar counterparts and aligns with standard naming conventions by renaming mulqihi3_scalar to mulqihi3. The new instructions target modes like vnhi (vector narrow signed integer) and vnsi (vector narrow unsigned integer) to expand the multiplication capabilities for vector types.
- widening multiply
- A multiplication operation where the result has a larger data type than the operands. For example, multiplying two 16-bit integers to produce a 32-bit result.
- AMDGCN
- AMD Graphics Core Next. An instruction set architecture for AMD's GPUs.
- vector
- A data type that holds multiple elements of the same basic type, processed in parallel by GPU or SIMD instructions.