XTENSA: Revise REGNO_REG_CLASS macro for minimal register class mapping
Xtensa target now correctly maps register numbers to their minimal encompassing register class.
The REGNO_REG_CLASS macro for the Xtensa target has been revised to accurately map each hardware register number to its minimal register class. This is achieved by generating a mapping within xtensa_conditional_register_usage that references a new global array, xtensa_regno_to_class. This ensures that the compiler always selects the most specific register class for a given register, as recommended by GCC’s internal documentation.
In Details
The REGNO_REG_CLASS macro in GCC's backend is crucial for mapping a hard register number to the smallest register class that contains it. Previously, this mapping might have been imprecise for Xtensa. This commit implements xtensa_regno_to_class, a global array populated by xtensa_conditional_register_usage, to provide this minimal mapping. The REGNO_REG_CLASS macro now consults this array, ensuring adherence to the gccint requirement for minimal register class selection during register allocation and instruction selection.
- REGNO_REG_CLASS
- A GCC internal macro that returns the register class containing a given register number. It should return the smallest possible class.
- register class
- A set of registers that can be used interchangeably for a particular purpose or operand type.
- hard register
- A physical register available on the target processor.
- Xtensa
- A configurable processor architecture, often used in embedded systems, for which GCC provides specific target support.
- gccint
- The GCC Internals Manual, which documents the compiler's internal structure and algorithms.
- TARGET_CONDITIONAL_REGISTER_USAGE
- A GCC target hook that allows target-specific code to influence register usage based on various conditions.