Enable 128-bit vector smaxmin/umaxmin with SSE4.1
x86 vector operations smaxmin and umaxmin are now enabled for 128-bit vectors using SSE4.1, requiring int128.
This change enables 128-bit vector smaxmin and umaxmin operations for the x86 architecture using SSE4.1 instructions. These operations do not require AVX512VL or AVX512DQ extensions. The relevant test cases, vec-narrow-1.C and vec-narrow-minmax-2.C, are updated to compile with ‘-msse4’ and specify the int128 requirement for x86. Previously, these 128-bit operations were not available for ia32 even with the ‘-mmmx’ flag.
In Details
This commit modifies the definition of TARGET_MMX_WITH_SSE in mmx.md to enable 128-bit vector smaxmin and umaxmin operations, which are part of the SSE4.1 instruction set. The patterns now correctly use TI (128-bit) mode and require TARGET_SSE4_1 and TARGET_MMX_WITH_SSE. The TARGET_MMX_WITH_SSE macro is defined as (TARGET_64BIT && TARGET_SSE2), ensuring these operations are available on 64-bit targets with SSE2 support when SSE4.1 is enabled. Test cases are updated accordingly.
- SSE4.1
- A set of SIMD (Single Instruction, Multiple Data) instructions for x86 processors, introduced with Intel's Penryn core.
- int128
- Refers to operations or data types that handle 128 bits of data. In this context, it's for 128-bit vector operations.
- smaxmin/umaxmin
- SIMD instructions that compute the maximum or minimum of two signed (smaxmin) or unsigned (umaxmin) integer elements within vectors.
- MMXMODE14/MMXMODE24
- Register classes in GCC's machine description for MMX registers, likely related to 128-bit or 256-bit SIMD registers.
- TI mode
- A GCC internal mode representing a 128-bit integer type, used for SIMD operations.