RISC-V: Expose address computations for atomic memory operations
Improves RISC-V atomic operations by exposing address calculations for better optimization.
This change enhances the RISC-V backend by tightening operand predicates for atomic memory operations. This exposes the address computation to optimization passes like CSE, allowing them to better identify and fold redundant address calculations. Previously, an issue with instruction predicates prevented these optimizations, leading to suboptimal code generation for static memory accesses.
In Details
This patch addresses PR target/108031 by adjusting operand predicates on RISC-V atomic memory operation patterns and expanders. By tightening these predicates to match the actual required simple memory indirect operands, the address calculation is now exposed to later optimization passes such as CSE (Common Subexpression Elimination). Previously, wider predicates led to the address computation remaining folded into the memory reference, preventing CSE from identifying duplicate address calculations, especially in cases involving static storage objects and adjacent structure fields.
- CSE
- Common Subexpression Elimination. An optimization pass that identifies identical expressions that appear multiple times in code and replaces subsequent occurrences with the result of the first computation, reducing redundant work.
- static storage
- Memory allocated for variables that have a fixed address throughout the program's execution. This includes global variables, static local variables, and static global variables.
- atomic memory operations
- Memory operations that are guaranteed to execute indivisibly, meaning they appear to occur instantaneously from the perspective of other threads or processors. This is crucial for maintaining data integrity in concurrent programming.
- operand predicates
- Conditions or constraints applied to the operands of an instruction in a compiler's instruction set architecture (ISA) description. These predicates define valid forms and types for operands, guiding instruction selection and optimization.