Cost SAD and ABD reductions accurately for AArch64 SIMD vs SVE.
AArch64 cost model now reflects the true performance of SAD/ABD reductions for Adv.SIMD and SVE.
The AArch64 backend’s cost model has been updated to accurately reflect the performance of Signed Absolute Difference (SAD) and Absolute Difference (ABD) reduction operations. This change accounts for extra work required by Adv.SIMD for 128-bit vectors and the more efficient SVE approach using udot, ensuring the compiler makes better vectorization and instruction selection decisions.
In Details
The AArch64 vector cost model in aarch64.cc is updated to correctly cost SAD_EXPR and SAD-style ABD reductions. For 128-bit Adv.SIMD, the cost now includes building the result from two 64-bit halves. For SVE, the path using uabd and udot is considered, while the fallback Adv.SIMD sequence using uabdl/uabal is charged appropriately. This synchronization impacts statement costing and the issue model for scalar profitability and vector-loop comparisons.
- SAD
- Signed Absolute Difference. An operation that calculates the absolute difference between two numbers and returns a signed result.
- ABD
- Absolute Difference. An operation that calculates the absolute difference between two numbers.
- Adv.SIMD
- Advanced Single Instruction Multiple Data. ARM's SIMD instruction set, often referred to as NEON.
- SVE
- Scalable Vector Extension. An ARM instruction set architecture extension that provides vectors of variable length.
- cost model
- A component of the compiler that estimates the performance cost of different code sequences or instructions to guide optimization decisions.
- udot
- An instruction in ARM's SVE that performs a dot product operation, often used for widening sums.