RISC-V: Disallow unsupported Zvabd patterns for specific SEW.
Enforces Zvabd specification by disallowing unsupported SEW values for vabd/vwabda patterns.
This commit refines the RISC-V vector code generation to adhere strictly to the Zvabd extension’s specification. It disallows the generation of vabd and vwabda instructions for unsupported Single-Element Widths (SEW), specifically limiting them to SEW 8 or 16 as defined by the standard. This prevents the creation of invalid or non-standard vector operations.
In Details
This change enforces the RISC-V Zvabd specification, which limits vabd[u] and vwabda[u] to SEW 8 or 16. It modifies the autovec-opt.md and vector.md files to restrict the allowed modes for these patterns. For example, (*vwabda<su><mode>) is now limited to VWEXTI_HS, and (<su>abd<mode>3) to VI_QH. New iterators in vector-iterators.md also help manage these constraints.
- Zvabd
- A RISC-V vector extension that provides instructions for calculating the absolute difference of vector elements.
- SEW
- Single-Element Width. In RISC-V vector processing, SEW defines the bit-width of individual elements within a vector register.
- vabd
- Vector Absolute Difference. A type of vector instruction that computes the absolute difference between corresponding elements of two vectors.
- vwabda
- Vector Widening Absolute Difference Add. A vector instruction that performs a widening absolute difference and adds the result to another vector.