THURSDAY, SEPTEMBER 24, 2026
amdgcn
amdgcn: Fix 64-bit vector multiply bug
Corrects a mathematical error in the 64-bit vector multiply operation for the AMD GCN architecture.
A bug in the compiler’s handling of 64-bit vector multiplication on AMD GCN GPUs has been fixed. The erroneous ‘hi*hi’ step in the multiplication logic has been removed, ensuring correct results for these operations.
In Details
Fixes a bug in the AMD GCN backend related to DImode (64-bit integer) vector multiplication. The specific issue was an erroneous 'hi*hi' step present in the mul<mode>3, mul<mode>3_dup, mul<mode>3_exec, and mul<mode>3_dup_exec patterns in gcn-valu.md. Removing this incorrect step restores proper mathematical behavior for 64-bit vector multiplications.
For Context
- amdgcn
- GCC's target backend for AMD's Graphics Core Next (GCN) architecture, used in their GPUs.
- DImode
- GCC's internal mode representing a 64-bit integer data type.
- vector multiply
- A multiplication operation performed on multiple data elements (lanes) within vector registers simultaneously.
- RTL pattern
- A template in GCC's Register Transfer Language used to describe how a specific machine instruction or operation is implemented on a target architecture.