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OCTOBER 6, 2026
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amdgcn

amdgcn: Add vector count leading zeros/ones instructions

Vector versions of count leading zeros/ones instructions are now available for AMD GPUs.

This commit adds vector counterparts for the scalar count leading zeros (ctz) and count leading ones (clz) instructions on AMD GPUs. Previously, only scalar versions were available. This enhancement provides more complete bit manipulation capabilities for vector data types on the AMDGPU architecture.

In Details

The AMDGPU backend gains vector support for count leading zeros (ctz) and count leading ones (clz) instructions, previously only available in scalar form. This is achieved by adding new machine definitions in gcn-valu.md and gcn.md that handle vector operations for these bit manipulation functions. The commit also introduces a new target feature TARGET_RDNA3_PLUS and updates machine descriptions for RDNA 3 and later, enabling these vector instructions for modern AMD GPU architectures.

For Context
ctz
Count Trailing Zeros. An instruction that counts the number of zero bits from the least significant bit up to the first set bit.
clz
Count Leading Zeros. An instruction that counts the number of zero bits from the most significant bit down to the first set bit.
AMDGCN
AMD Graphics Core Next. An instruction set architecture for AMD's GPUs.
vector
A data type that holds multiple elements of the same basic type, processed in parallel by GPU or SIMD instructions.
Filed Under: amdgpubit manipulationinstruction selection