Fix FP16 combine patterns for aarch64, preventing assembly failures.
Corrects aarch64 assembly generation for FP16 types, avoiding failures when the fp16 extension is not enabled.
This commit addresses an issue on aarch64 where the combinez patterns for scalar and partial vector FP16 types incorrectly used the FMOV instruction even when the fp16 extension was not available. This led to assembly failures. The fix specializes these patterns for HF and BF modes and uses the INS instruction as a fallback, resolving the bug reported in PR126983.
In Details
The aarch64_combinez patterns in config/aarch64/aarch64-simd.md were indiscriminately using FMOV for scalar FP16 modes, causing assembly failures when the fp16 extension was absent. This change splits the patterns into HFBF variants and uses INS as a fallback, fixing PR126983. It also adds a test case vec-init-23-nofp16.c to verify assembly without the extension.
- FP16
- A floating-point number format that uses 16 bits to represent a value. It offers reduced memory usage and potentially faster computation compared to FP32 or FP64, but with lower precision and range.
- aarch64
- The 64-bit ARM architecture, commonly used in mobile devices and increasingly in servers and embedded systems.
- combinez
- A GCC pass or pattern matching mechanism that attempts to combine multiple simple instructions into a single, more complex instruction, or to simplify existing instructions.
- FMOV
- A floating-point move instruction found on many architectures, used to copy floating-point values.
- INS
- An instruction, possibly 'insert', used in ARM assembly to insert bits into a register, often used for constructing vector elements or manipulating bitfields.