Support FCCMP and FCCMPE for _Float16
GCC now supports half-precision floating-point conditional comparisons on AArch64.
This commit adds support for half-precision floating-point conditional compare instructions (FCCMP and FCCMPE) on the AArch64 architecture when the FEAT_FP16 extension is available. Previously, these instructions only supported single-precision and double-precision types. The change updates the conditional-compare patterns and expansion hooks to correctly handle HFmode (_Float16) and improves code generation for comparisons involving half-precision floats. New test cases verify the functionality.
In Details
The AArch64 backend patterns for conditional compare instructions (aarch64.md) were extended to support HFmode (half-precision float) using GPF_F16. The aarch64_gen_ccmp_first and aarch64_gen_ccmp_next functions in config/aarch64/aarch64.cc were updated to handle HFmode, rejecting it if FEAT_FP16 is unavailable. The stype attribute is used to maintain single-precision scheduling type for HFmode.
- FCCMP
- AArch64 assembly instruction that performs a conditional compare between two floating-point registers.
- FCCMPE
- AArch64 assembly instruction that performs a conditional compare between two floating-point registers, with exceptions for NaN values.
- _Float16
- A C data type representing a 16-bit (half-precision) floating-point number, as defined by ISO/IEC TS 18661-3.
- AArch64
- The 64-bit ARM architecture, commonly used in mobile devices and servers. GCC supports code generation for this architecture.
- FEAT_FP16
- An ARM architecture feature that enables support for 16-bit floating-point operations.
- HFmode
- GCC's internal mode representing a half-precision floating-point number (16 bits).
- GPF_F16
- A target-specific flag or mode used in AArch64 backend patterns to indicate operations on half-precision floating-point numbers.
- stype
- An attribute in GCC's machine description that specifies the scheduling type of a data type, influencing instruction scheduling.