RISC-V: Add CPU identification registers for 6 cores

Identification registers (MVENDORID, MARCHID, MIMPID) are added for six RISC-V cores.

By Kito Cheng August 20, 2026 committed

GCC’s RISC-V backend now includes the MVENDORID, MARCHID, and MIMPID identification registers for six specific RISC-V cores. This enhancement supports the automatic detection of CPU types for tuning and optimization purposes, enabling features like -mtune=native.

In Details

This commit populates the RISCV_CORE definition in riscv-cores.def with the MVENDORID, MARCHID, and MIMPID values for six RISC-V cores: sifive-u74, sifive-p550, sifive-p870-d, spacemit-x60, spacemit-x100, and spacemit-a100. This data is crucial for runtime CPU identification, forming the basis for features like -mcpu=native.

Filed Under: risc-vcpu

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