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OCTOBER 6, 2026
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risc-v

RISC-V: Fix sub-Pmode index in vec_set/vec_extract

Fixes incorrect slide amount calculation for variable-indexed vector operations on RISC-V.

This patch corrects an issue in RISC-V vector operations where variable-indexed element accesses were being mishandled. Previously, gen_lowpart incorrectly reinterpreted sub-Pmode indices, leading to wrong slide amounts in vslideup/vslidedown instructions. The fix uses convert_to_mode to zero-extend these indices, ensuring correct code generation.

In Details

On RISC-V, when gimple-isel lowers variable-indexed vector element access to .VEC_SET or .VEC_EXTRACT, the index might be narrower than Pmode. The expanders incorrectly used gen_lowpart, which only reinterprets the register, discarding source-level truncation. This led to the full 64-bit value being used as the slide amount for vslideup/vslidedown. This change rectifies this by zero-extending sub-Pmode indices using convert_to_mode.

For Context
Pmode
A machine mode used in GCC, often representing a pointer-sized integer, used for indices and addresses.
gimple-isel
The GIMPLE Intermediate Representation (IR) instruction selector pass in GCC, responsible for converting GIMPLE to RTL (Register Transfer Language).
vec_set
A GIMPLE intrinsic or internal operation representing setting an element in a vector.
vec_extract
A GIMPLE intrinsic or internal operation representing extracting an element from a vector.
RISC-V
An open-standard instruction set architecture (ISA) based on reduced instruction set computer principles.
Filed Under: risc-vvectorizationcompilerbugfix