Arm NEON intrinsics incorrectly reject zero shift amounts.
Arm NEON widening shift-left intrinsics now correctly handle zero shifts by using VMOVL.
Arm NEON widening shift-left intrinsics (vshll_n) that accept a zero shift amount were previously rejected by the assembler because the VSHLL instruction encoding does not support a zero shift. This change modifies the intrinsic to emit VMOVL for a zero shift, which has the same semantics and is correctly encoded, improving code quality for valid ACLE code. Additionally, it uses the signless form for intrinsics when the shift amount equals the element size.
In Details
The NEON VSHLL instruction on ARM targets does not support a shift amount of zero. However, the ACLE specification defines zero shift for widening shifts as a move operation. This commit modifies the neon-vshll intrinsic in GCC's NEON md file to emit VMOVL for a zero shift amount, aligning with ACLE semantics and resolving assembler errors. It also corrects the mnemonic for cases where the shift amount equals the element size to use the signless form.