RISC-V: Avoid emitting shNadd with a virtual register base
RISC-V code generation avoids shNadd instruction with virtual register bases to enable better frame offset folding.
The RISC-V code generator now avoids emitting the shNadd instruction when its base register is a virtual register. This prevents the frame offset from being folded into the instruction later, which previously resulted in longer instruction sequences. The change simplifies generated code for certain stack access patterns.
In Details
In config/riscv/riscv.cc, the synthesize_add function is modified to prevent the generation of shNadd instructions when the base register is a virtual register. Previously, using a virtual register as the base for shNadd prevented subsequent frame offset folding, leading to less optimal code. The fix ensures that frame pointer relative addressing can be folded more effectively, simplifying instruction sequences for stack operations.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computer principles.
- shNadd
- A RISC-V instruction (part of the Zba extension) that performs a scaled-add operation, often used for address calculations.
- Virtual Register
- A temporary storage location used by the compiler during optimization. Virtual registers are not directly mapped to hardware registers and are managed by the compiler's register allocator.
- Frame Offset Folding
- An optimization where the offset from the frame pointer (or stack pointer) is directly incorporated into an address calculation instruction, often simplifying or reducing the number of instructions needed.
- Zba extension
- A RISC-V base extension that adds byte manipulation and address calculation instructions, including
shNadd.