RISC-V: Align slow unaligned access handling
Corrects handling of misaligned memory accesses on RISC-V to align with vector misalignment support.
This commit rectifies an issue in the RISC-V backend concerning the riscv_slow_unaligned_access function. Due to a recent addition of a vector mode check, this function was returning an inverted value for supported misaligned access. This led to the compiler incorrectly assuming that misaligned accesses were slow even when they were supported, particularly for -mtune=generic-ooo. The patch aligns the behavior of riscv_slow_unaligned_access with riscv_support_vector_misalignment to ensure correct handling of misaligned memory operations.
In Details
Aligns riscv_slow_unaligned_access with riscv_support_vector_misalignment. Previously, the former incorrectly returned the inverted result of the latter due to a new vector mode check, causing it to incorrectly signal slow misaligned accesses even when vector misalignment was supported. This fix ensures consistent behavior for misaligned memory access handling on RISC-V targets.
- RISC-V
- An open standard instruction set architecture (ISA) based on Reduced Instruction Set Computing principles.
- unaligned access
- A memory access where the memory address is not aligned to the natural boundary of the data type being accessed (e.g., accessing a 4-byte integer at an address not divisible by 4).
- vector mode
- Refers to the use of vector instructions, which operate on multiple data elements simultaneously.
- -mtune=generic-ooo
- A GCC compiler flag that specifies the target CPU architecture and enables out-of-order execution optimizations, potentially affecting instruction scheduling and handling of certain operations like misaligned accesses.
- misalignment
- The condition where a memory address does not fall on a boundary required by the size of the data being accessed.