RISC-V: Add TImode and OImode move expanders.
RISC-V now supports TImode and OImode move operations, addressing issues with vector register sub-parts.
RISC-V support has been enhanced with the addition of TImode and OImode move expanders. This resolves an issue where sub-parts of vector registers, such as (subreg:TI (reg:V4SF R) 0), were valid but could not be split or moved. The changes define necessary move operations to enable these capabilities on the RISC-V architecture.
In Details
This commit adds TImode and OImode move expanders to the RISC-V backend, addressing a gap identified in commit ec58d736cd57. Specifically, it implements riscv_subpart, spill_subreg_move, and riscv_split_quadword_move to handle unsplittable subregisters for vector types. The new movti and movoi patterns in riscv.md fulfill the requirement stated in PR target/124996 and PR middle-end/125390 for targets defining REGMODE_NATURAL_SIZE to provide appropriate integer move patterns.
- TImode
- A GCC machine mode representing a 128-bit integer type. It is often used for vector operations or larger integer types.
- OImode
- A GCC machine mode representing a 256-bit integer type. Similar to TImode, it's typically used for large integer or vector data.
- move expander
- Code within the compiler's backend that generates machine instructions for moving data between registers or memory. For complex modes, these expanders break down the operation into simpler instructions.
- subreg
- A machine mode representing a subset of bits within a larger register. This is used to access parts of a vector register or other larger data types stored in registers.