RISC-V vector instructions allow register group overlap.
RISC-V vector instructions vwmacc.vx and vwmaccu.vx now support register group overlap.
The RISC-V vector extension (RVV) has been updated to allow register group overlap for the vwmacc.vx and vwmaccu.vx instructions. This change enables more flexible register allocation and potentially better performance by allowing these instructions to use registers that might otherwise be considered overlapping.
New test cases have been added to verify this functionality across various data types and vector sizes, ensuring correct behavior and preventing regressions.
In Details
The RISC-V Vector Extension (RVV) previously restricted certain dual-widen ternary instructions, like vwmacc.vx, from using overlapping register groups. This commit modifies the vector instruction patterns in config/riscv/vector.md to leverage the Wvr constraint, permitting register overlap similar to how vwmacc.vv already operates. This change aims to improve register pressure and scheduling flexibility within the RVV instruction set.
- RISC-V Vector Extension (RVV)
- An extension to the RISC-V instruction set architecture that adds support for vector processing, allowing operations on multiple data elements simultaneously for improved performance in data-parallel tasks.
- vwmacc.vx
- A specific RISC-V vector instruction that performs a widened multiply-accumulate operation with a vector source and a scalar source, storing the result in a vector register.
- register group overlap
- In the context of vector registers, this refers to a situation where an instruction can use registers that have overlapping parts or are adjacent, providing more flexibility in register allocation and potentially allowing for more efficient instruction scheduling.
- Wvr constraint
- A constraint used in GCC's instruction patterns to specify that a register operand must be compatible with vector register usage, allowing for register overlap where applicable.