RISC-V: Fix zvl effective-target check cache collision
RISC-V vector length checks now use unique cache properties to avoid incorrect results.
Vector length (zvl) checks for RISC-V’s vector extension (RVV) incorrectly used a shared cache property. This could lead to unsupported tests running or supported tests being skipped because a check for one vector length (e.g., VLEN=128) might incorrectly cache results for another (e.g., VLEN=256). This change assigns a unique property to each check_runtime call for different zvl configurations, resolving the cache collision.
In Details
The check_runtime property in target-supports.exp is used for caching results of target checks. For RISC-V's RVV extension, multiple checks (rvv_zvl*_ok) were sharing the same check_runtime property, leading to cache collisions. This commit differentiates the check_runtime property for each specific zvl check (e.g., rvv_zvl128b_ok, rvv_zvl256b_ok), ensuring that each check's result is cached independently. This is relevant for testing various vector lengths and configurations within the testsuite.
- RVV
- RISC-V Vector extension, a set of instructions for processing data in parallel using vectors.
- zvl
- Vector length specifier for RISC-V, indicating the active vector length.
- target-supports.exp
- A Tcl script in GCC's testsuite used to check target machine support for various features.
- check_runtime
- A variable or property within the
target-supports.expscript that caches the result of a target feature check to avoid redundant computations.